W9425G6EH_0812 Datasheet, PDF (26/54 Pages) Winbond – 4 M × 4 BANKS × 16 BITS DDR SDRAM

W9425G6EH
9.5 DC Characteristics
SYM.
PARAMETER
MAX.
UNIT NOTES
-4
-5/-5I -6/-6I
Operating current: One Bank Active-Precharge; tRC = tRC min;
IDD0 tCK = tCK min; DQ, DM and DQS inputs changing twice per clock 110
110
110
mA
7
cycle; Address and control inputs changing once per clock cycle
Operating current: One Bank Active-Read-Precharge; Burst = 2;
IDD1 tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and
150
150
150
7, 9
control inputs changing once per clock cycle.
Precharge Power Down standby current: All Banks Idle; Power
IDD2P down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ,
20
20
20
DQS and DM
Idle floating standby current: CS > VIH min; All Banks Idle;
IDD2F _{CKE > VIH min; Address and other control inputs changing once}
45
45
45
7
per clock cycle; Vin = Vref for DQ, DQS and DM
Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH
IDD2N ^{min; tCK = tCK min; Address and other control inputs changing}
45
45
45
7
once per clock cycle; Vin > VIH min or Vin < VIL max for DQ,
DQS and DM
Idle quiet standby current: CS > VIH min; All Banks Idle; CKE
IDD2Q _{> VIH min; tCK = tCK min; Address and other control inputs}
40
40
40
7
stable; Vin > VREF for DQ, DQS and DM
IDD3P
Active Power Down standby current: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min
20
20
20
Active standby current: CS > VIH min; CKE > VIH min; One
IDD3N ^{Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM}
70
70
70
7
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Operating current: Burst = 2; Reads; Continuous burst; One
IDD4R Bank Active; Address and control inputs changing once per
210
180
170
7, 9
clock cycle; CL=3; tCK = tCK min; IOUT = 0mA
Operating current: Burst = 2; Write; Continuous burst; One Bank
IDD4W
Active; Address and control inputs changing once per clock
cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing
210
180
170
7
twice per clock cycle
IDD5 Auto Refresh current: tRC = tRFC min
190
190
190
7
IDD6 Self Refresh current: CKE < 0.2V
3
3
3
Random Read current: 4 Banks Active Read with activate every
IDD7
20nS, Auto-precharge Read every 20 nS; Burst = 4; tRCD = 3;
IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock
300
300
300
cycle; Address changing once per clock cycle
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Publication Release Date:Dec. 03, 2008
Revision A08