W9425G6EH_0812 Datasheet, PDF (16/54 Pages) Winbond – 4 M × 4 BANKS × 16 BITS DDR SDRAM

W9425G6EH
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1
BA0
0
0
0
1
1
x
A12-A0
Regular MRS Cycle
Extended MRS Cycle
Reserved
7.10.6 Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
0
1
DLL
Enable
Disable
2) Output Driver Size Control field (A6, A1)
The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode
Register Set (EMRS) as the following:
A6
A1
BUFFER STRENGTH
0
0
100% Strength
0
1
60% Strength
1
0
Reserved
1
1
30% Strength
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Publication Release Date:Dec. 03, 2008
Revision A08