W9425G6EH_0812 Datasheet, PDF (2/54 Pages) Winbond – 4 M × 4 BANKS × 16 BITS DDR SDRAM

W9425G6EH
7.10.3 CAS Latency field (A6 to A4)................................................................................................16
7.10.4 DLL Reset bit (A8) ................................................................................................................16
7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) ........................................16
7.10.6 Extended Mode Register field ..............................................................................................16
7.10.7 Reserved field ......................................................................................................................17
8. OPERATION MODE ....................................................................................................................................18
8.1 Simplified Truth Table ......................................................................................................................18
8.2 Function Truth Table ........................................................................................................................19
8.3 Function Truth Table for CKE...........................................................................................................22
8.4 Simplified Stated Diagram ................................................................................................................23
9. ELECTRICAL CHARACTERISTICS ............................................................................................................24
9.1 Absolute Maximum Ratings..............................................................................................................24
9.2 Recommended DC Operating Conditions ........................................................................................24
9.3 Capacitance .....................................................................................................................................25
9.4 Leakage and Output Buffer Characteristics......................................................................................25
9.5 DC Characteristics ...........................................................................................................................26
9.6 AC Characteristics and Operating Condition ....................................................................................27
9.7 AC Test Conditions ..........................................................................................................................28
10. SYSTEM CHARACTERISTICS FOR DDR SDRAM.....................................................................................31
10.1 Table 1: Input Slew Rate for DQ, DQS, and D M .............................................................................31
10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate ...............................................................31
10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate....................................................31
10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate ....................................31
10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)........................................................31
10.6 Table 6: Output Slew Rate Matching Ratio Characteristics ..............................................................32
10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins..............................32
10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins...............................33
10.9 System Notes: ..................................................................................................................................34
11. TIMING WAVEFORMS ................................................................................................................................36
11.1 Command Input Timing ....................................................................................................................36
11.2 Timing of the CLK Signals ................................................................................................................36
11.3 Read Timing (Burst Length = 4) .......................................................................................................37
11.4 Write Timing (Burst Length = 4) .......................................................................................................38
11.5 DM, DATA MASK (W9425G6EH).....................................................................................................39
11.6 Mode Register Set (MRS) Timing.....................................................................................................40
11.7 Extend Mode Register Set (EMRS) Timing ......................................................................................41
11.8 Auto-precharge Timing (Read Cycle, CL = 2) ..................................................................................42
11.9 Auto-precharge Timing (Read cycle, CL = 2), continued..................................................................43
11.10 Auto-precharge Timing (Write Cycle) ...............................................................................................44
Publication Release Date:Dec. 03, 2008
-2-
Revision A08