W83194R-17 Datasheet, PDF (2/21 Pages) Winbond – 100MHZ AGP CLOCK FOR SIS CHIPSET

W83194R-17/-17A
3.0 BLOCK DIAGRAM
PLL2
~
X1
XTAL
X2
OSC
¡Ò₂
STOP
FS(0:2) ³
MODE
CPU3.3#_2.5
CPU_STOP#
PCI_STOP#
SDATA
SCLK
PLL1
Spread
Spectrum
LATCH
~⁵
POR
Control
Logic
Config.
Reg.
STOP
PCI
clock STOP
Divder
PRELIMINARY
48MHz
24MHz
REF(0:1)
2
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
3
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Vdd
1
REF0/CPU3.3#_2.5
2
Vss
3
Xin
4
Xout
5
Vddq3
6
PCICLK_F/*FS1
7
PCICLK0/*FS2
8
Vss
9
PCICLK1
10
PCICLK2
11
PCICLK3
12
PCICLK4
13
Vddq3
14
AGP0
15
Vss
16
CPU_STOP#/SDRAM11
17
PCI_STOP#/SDRAM10
18
Vddq3
19
SDRAM 9
20
SDRAM 8
21
Vss
22
SDATA
SDCLK
23
24
-2-
48
Vddq2
47
AGP1
46
REF1
45
Vss
44
CPUCLK0
43
CPUCLK1
42
Vddq2b
41
CPUCLK2
40
CPUCLK3
39
Vss
38
SDRAM 0
37
SDRAM 1
36
Vddq3
35
SDRAM 2
34
SDRAM 3
33
Vss
32
SDRAM 4
31
SDRAM 5
30
Vddq3
29
SDRAM 6
28
SDRAM 7
27
Vss
26
48MHz/*FS0
25
24MHz/*MODE
Publication Release Date: Sep. 1998
Revision 0.20