W83194R-17 Datasheet, PDF (11/21 Pages) Winbond – 100MHZ AGP CLOCK FOR SIS CHIPSET

W83194R-17/-17A
PRELIMINARY
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
x
- Reserved
6
x
- Reserved
5
x
- Reserved
4
x
- Reserved
3
1
17 SDRAM11 (Active / Inactive)
2
1
18 SDRAM10 (Active / Inactive)
1
1
20 SDRAM9 (Active / Inactive)
0
1
21 SDRAM8 (Active / Inactive)
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
x
- Reserved
6
x
- Reserved
5
x
- Reserved
4
1
47 AGP1 (Active / Inactive)
3
x
- Reserved
2
x
- Reserved
1
1
46 REF1 (Active / Inactive)
0
1
2 REF0 (Active / Inactive)
8.3.7 Register 6: Reserved Register
Bit @PowerUp Pin
7
x
- Reserved
6
x
- Reserved
5
x
- Reserved
4
x
- Reserved
3
x
- Reserved
2
x
- Reserved
1
x
- Reserved
0
x
- Reserved
Description
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Publication Release Date: Sep. 1998
Revision 0.20