English
Language : 

W83194R-17 Datasheet, PDF (1/21 Pages) Winbond – 100MHZ AGP CLOCK FOR SIS CHIPSET
W83194R-17/-17A
1.0 GENERAL DESCRIPTION
100MHZ AGP CLOCK FOR SIS CHIPSET
The W83194R-17/-17A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel PentiumII, PentiumPro , AMD or Cyrix. Eight different
frequency of CPU, AGP and PCI clocks are externally selectable with smooth transitions. The
W83194R-17/-17A provides AGP clocks especially for clone chipset. The highest CPU frequency
provided by the W83194R-17 is up to 100MHz, but the one of W83194R-17A is up to 133MHz.
The W83193R-17/-17A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.5% or 1.5% center type spread spectrum to reduce EMI.
The W83194R-17/-17A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads
as maintaining 50¡Ó5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz
provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• Supports Pentium™, Pentium™ Pro, Pentium™ II, AMD and Cyrix CPUs with I2C.
• 4 CPU clocks
• 12 SDRAM clocks for 3 DIMMs
• Two AGP clocks
• 6 PCI synchronous clocks.
• Optional single or mixed supply:
(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd =Vddq2 = Vddq3 = 3.3V, Vddq2b = 2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)
• Smooth frequency switch with selections from 60 MHz to 133 MHz CPU
• I2C 2-Wire serial interface and I2C read back
• ¡Ó0.5% or ¡Ó1.5% center type spread spectrum function to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• MODE pin for power Management
• 48 MHz for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Sep. 1998
-1-
Revision 0.20