W19B320BT Datasheet, PDF (19/56 Pages) Winbond – 2.7~3.6-volt write (program and erase) operations

W19B320BT/B DATASHEET
If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program
command sequence is written, and then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling when the Embedded
Program algorithm is complete.
Please also refer to DQ2: Toggle Bit II.
6.3.4 DQ2: Toggle Bit II
When used with DQ6, the “Toggle Bit II” on DQ2 indicates whether a particular sector is actively erasing
(i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final #WE pulse in the command sequence.
DQ2 toggles as the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot distinguish that
whether the sector is actively erasing or is erase-suspended. By comparison, DQ6 indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for
erasure. Therefore, both status bits are required for sector and mode information.
6.3.5 Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row
to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of
the toggle bit after the first read. While after the second read, the system would compare the new value of
the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or
erasure operation. The system can read array data on DQ0-DQ7 on the following read cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the
system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erasure operation. If it is still toggling, the device did not complete the operation,
and the system must write the reset command to return to reading array data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status
as described in the previous paragraph. Alternatively, the system may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the
status of the operation.
6.3.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device
stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
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Publication Release Date:Dec. 25, 2007
Revisionv A3