W83194BR-903_06 Datasheet, PDF (16/26 Pages) Winbond – STEPLESS VIA PT/PM MAIN CLOCK GENERATOR

W83194BR-903/W83194BG-903
Table-2 CPU, AGP, PCI divider ratio selection Table
LSB
AGP
MSB
Bit5
0
1
00
Bit2/
0
Div6
Div7
Div2
Bit9
1
Div10
Div12
Div8
CPU
Bit1, 0
01
10
Div3
Div4
Div8
Div8
11
Div6
Div8
7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh)
BIT
NAME
7 EN_MN_PROG
6 Reserved
5 Reserved
4 Reserved
3 IVAL<3>
2 IVAL<2>
1 IVAL<1>
0 IVAL<0>
PWD
DESCRIPTION
0 0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ
(Reg0 - bit 0).
0 Reserved
0 Reserved
0 Reserved
1 Charge pump current selection
1
1
1
7.15 Register 14: Control (Default: 0Ah)
BIT
NAME
7 CPUT_DRI
6 Reserved
5 SPCNT [5]
4 SPCNT [4]
3 SPCNT [3]
2 SPCNT [2]
1 SPCNT [1]
0 SPCNT [0]
PWD
DESCRIPTION
0 CPUT output state in during POWER DOWN or Stop mode assertion.
1: Driven (2*Iref),
0: Tristate (Floating)
CPUC always tri-state (floating) in power down Assertion.
0 Reserved
0 Spread Spectrum Programmable time, the resolution is 280ns. Default
0 ^{period is 11.8us}
1
0
1
0
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