W83194BR-903_06 Datasheet, PDF (15/26 Pages) Winbond – STEPLESS VIA PT/PM MAIN CLOCK GENERATOR

W83194BR-903/W83194BG-903
7.11 Register 10: M/N Program (Default: BBh)
BIT
NAME
PWD
DESCRIPTION
7 N_DIV [9]
1 Programmable N divisor bit 9.
6 N3<6>
0 Programmable N3 divisor bit 6 ~0 for programmable 25M clocks.
5 N3<5>
4 N3<4>
3 N3<3>
1 M3=10000 (Fix)
1 ^{Frequency range: 21.7M ~ 28.8M}
1 ^{Resolution: 56K}
2 N3<2>
0
1 N3<1>
1
0 N3<0>
1
7.12 Register 11: Spread Spectrum Programming (Default: 0Bh)
BIT
NAME PWD
DESCRIPTION
7 SP_UP [3]
0 Spread Spectrum Up Counter bit 3 ~ bit 0.
6 SP_UP [2]
0
5 SP_UP [1]
0
4 SP_UP [0]
0
3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 ~ bit 0
2 SP_DOWN [2] 0 2’s complement representation.
1 SP_DOWN [1] 1 ^{Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000}
0 SP_DOWN [0] 1
7.13 Register 12: Divisor and Step-less Enable Control (Default: FBh)
BIT
NAME PWD
DESCRIPTION
7 Reserved
1 Reserved
6 DS9
5 DS5
1 Define the AGP divider ratio
1 ^{Table-2 integrate the all divider configuration}
4 Reserved
1 Reserved
3 Reserved
1
2 DS2
0 Define the CPU divider ratio
1 DS1
1 Refer to Table-2
0 DS0
1
- 11 -
Publication Release Date: May 2006
Revision 1.0