W9816G6JH Datasheet, PDF (15/42 Pages) Winbond – 512K X 2 BANKS X 16 BITS SDRAM

W9816G6JH
9.5 AC Characteristics
(VDD = 3.3V ± 0.3V for -5/-6/-6I, VDD = 2.7V to 3.6V for -7/-7I, TA = 0 to 70°C for -5/-6/-7, TA= -40 to 85°C for -6I//-7I)
PARAMETER
-5
SYM.
MIN. MAX.
-6/-6I
MIN. MAX.
-7/-7I
MIN. MAX.
UNIT NOTES
Ref/Active to Ref/Active Command Period t_RC
Active to Precharge Command Period
t_RAS
Active to Read/Write Command Delay
Time
t_RCD
55
60
40 100000 42
15
18
65
100000 45 100000 _nS
20
Read/Write(a) to Read/Write(b)Command
Period
t_CCD
1
1
1
t_CK
Precharge to Active(b) Command Period t_RP 15
18
Active(a) to Active(b) Command Period t_RRD 10
12
18
nS
14
CL* = 2
2
2
Write Recovery Time
t_WR
CL* = 3
2
2
2
t_CK
2
CLK Cycle Time
CL* = 2
7 1000 8
t_CK
CL* = 3
5 1000 6
1000 10 1000
1000 7 1000
CLK High Level Width
t_CH
2
2
2
8
CLK Low Level Width
t_CL
2
2
2
8
CL* = 2
6
5.5
5.5
Access Time from CLK
t_AC
9
CL* = 3
4.5
5
5
Output Data Hold Time
t_OH
2
2
2
9
Output Data High
Impedance Time
CL* = 2
6
5.5
5.5
t_HZ
7
CL* = 3
4.5
5
5
Output Data Low Impedance Time
t_LZ
0
0
0
nS
9
Power Down Mode Entry Time
t_SB
0
5
0
6
0
7
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
t_DS 1.5
1.5
1.5
8
t_DH 0.7
0.7
1
8
t_AS 1.5
1.5
1.5
8
Address Hold Time
t_AH 0.7
0.7
1
8
CKE Set-up Time
t_CKS 1.5
1.5
1.5
8
CKE Hold Time
t_CKH 0.7
0.7
1
8
Command Set-up Time
t_CMS 1.5
1.5
1.5
8
Command Hold Time
t_CMH 0.7
0.7
1
8
Refresh Time (2K Refresh Cycles)
t_REF
32
32
32 mS
Mode Register Set Cycle Time
t_RSC
2
2
2
t_CK
Exit self refresh to ACTIVE command
t_XSR 70
72
75
nS
* CL = CAS Latency
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Publication Release Date: Jun. 24, 2014
Revision: A01