W29GL032C_13 Datasheet, PDF (14/68 Pages) Winbond – 32M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL032C
7.2.7 Byte/Word Selection
To choose between the Byte or Word mode, the #BYTE input pin is used to select how the data is
input/output on the Data IO pins and the organization of the array data. If the #BYTE pin is driven
High, Word mode will be selected and all 16 Data IO pins will be active. If the #BYTE is pulled Low,
Byte mode will be active and only Data IO DQ[7:0] will be active. The remaining Data IO pins
(DQ[14:8]) will be in a high impedance state and DQ15 becomes the A-1 address input pin.
7.2.8 Automatic Programming of the Memory Array
To program the memory array in Byte or Word mode, refer to the Instruction Definition Tables for
correct cycle defined instructions that include the 2 unlocking instruction cycles, the A0h program cycle
instruction and subsequent cycles containing the specified address location and the byte or word
desired data content, followed by the start of the embedded algorithm to automatically program the
array.
Once the program instruction sequence has been executed, the internal state machine commences
execution of the algorithms and timing necessary for programming and cell verification. Included in this
operation is generating suitable program pulses, checking cell threshold voltage (V_T) margins, and if
any cells do not pass verification or have acceptable margins, repetitive program pulse sequence will
be cycled again. The internal process mechanisms will protect cells that do pass margin and
verification tests from being over-programmed by prohibiting further program pulses to passing cells
as failing cells continue to be run through the internal programming sequence until the pass.
This feature allows the user to only perform the auto-programming sequence once and the device
state machine takes care of the program and verification process.
Array bits during programming can only change a bit status of “1” (erase state) to a “0” (programmed
state). It is not possible to do the reverse with a programming operation. This can only be done by first
performing an erase operation. Keep in mind, the internal write verification only checks and detects
errors in cases where a “1” is not successfully programmed to “0”.
During the embedded programming algorithm process any commands written to the device will be
ignored, except hardware reset or program suspend instruction. Hardware reset will terminate the
program operation after a period of time, not to exceed 10µs. If in the case a Program Suspend was
executed, the device will enter the programs suspend read mode. When the embedded program
algorithm is completed or the program is terminated by a hardware reset, the device will return to
Read mode.
The user can check for completion by reading the following bits in the status register, once the
embedded program operation has started:
Status
DQ7
DQ6
DQ5
DQ1
RY/#BY¹
In progress
DQ7#
Toggling
0
0
0
Exceeded time
DQ7#
Toggling
1
N/A
0
limit
Table 7-3
Polling During Embedded Program Operation
Note:
1. RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
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