W29GL032C_13 Datasheet, PDF (13/68 Pages) Winbond – 32M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL032C
7.2.3 Device Reset Operation
Pulling the #RESET pin Low for a period equal to or greater than tRP will return the device to Read
mode. If the device is performing a program or erase operation, the reset operation will take at most a
period of tREADY1 before the device returns to Read mode. The RY/#BY pin will remain Low (Busy
Status) until the device returns to Read mode.
Note, the device draws larger current if the #RESET pin is held at voltages greater that GND+0.3V
and less than or equal to VIL. When the #RESET pin is held a GND±0.3V, the device only consumes
Reset (ICC5) current.
It is recommended to tie the system reset signal to the #RESET pin of the flash memory. This allows
the device to be reset with the system and puts it in a state where the system can immediately begin
reading boot code from it.
Executing the Reset instruction will reset the device back to the Read mode in the following situations:
• During an erase instruction sequence, before the full instruction set is completed.
• Sector erase time-out period
• Erase failed, while DQ5 is High.
• During program instruction sequence, before the full instruction set is completed, including the
erase-suspended program instruction.
• Program failed, while DQ5 is High as well as the erase-suspended program failure.
• Auto-select mode
• CFI mode
• The user must issue a reset instruction to reset the device back to the Read mode when the
device is in Auto-Select mode or CFI mode, or when there is a program or erase failure (DQ5
is High).
• When the device is performing a Programming (not program fail) or Erasing (Not erase fail)
function, the device will ignore reset commands.
7.2.4 Standby Mode
Standby mode is entered when both #RESET and #CE are driven to VCC ±300mV (inactive state).
(Note, if both pins are not within the EVIO ±0.3V, but at VIH, standby current will be greater.) At this
time output pins are placed in the high impedance state regardless of the state of the #WE or #OE
pins and the device will draw minimal standby current (ICC4). If the device is deselected during erase
or program operation, the device will draw active current until the operation is completed.
7.2.5 Output Disable Mode
The #OE pin controls the state of the Data IO pins. If #OE is driven High (VIH), all Data IO pins will
remain at high impedance and if driven Low, the Data IO pins will drive data ( #OE has no affect on
the RY/#BY output pin).
7.2.6 Write Operation
To execute a write operation, Chip Enable (#CE) pin is driven Low and the Output Enable (#OE) is
pulled high to disable the Data IO pins to a high impedance state. The desired address and data
should be present on the appropriate pins. Addresses are latched on the falling edge of either #WE or
#CE and Data is latched on the rising edge or either #CE or #WE. To see an example, please refer to
timing diagrams in Figure 8-5, Figure 8-15 or Figure 8-16. If an invalid write instruction, not defined in
this datasheet is written to the device, it may put the device in an undefined state.
Publication Release Date: August 2, 2013
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Revision H