W83195WG-413 Datasheet, PDF (12/27 Pages) Winbond – Winbond Clock Generator

5 CLREQB5#_Ctr
4 CLREQB4#_Ctr
3 CLREQB3#_Ctr
2 CLREQB0#_Ctr
1 PCIEN
0 Reserved
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
SRCCLK5 is controlled by the CLREQB# pin
0 1: Controllable
R/W
0: Uncontrollable
SRCCLK4 is controlled by the CLREQB# pin
0 1: Controllable
R/W
0: Uncontrollable
SRCCLK3 is controlled by the CLREQB# pin
0 1: Controllable
R/W
0: Uncontrollable
SRCCLK0 is controlled by the CLREQB# pin
0 1: Controllable
R/W
0: Uncontrollable
PCI0 output control
1 1: Enable
R/W
0: Disable
1 Reserved
R/W
7.5 Register 4: ( Default : FEh)
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
7 CPU2S_EN
6 CPU1S_EN
5 CPU0S_EN
4 REFEN<2>
3 REFEN<1>
2 REFEN<0>
1 F48EN
CPU_STOP# pin control.
1 1: Enable CPUCLK2 stop feature
0: Disable stop feature
CPU_STOP# pin control.
1 1: Enable CPUCLK1 stop feature
0: Disable stop feature
CPU_STOP# pin control.
1 1: Enable CPUCLK0 stop feature
0: Disable stop feature
PREF2 output control
1 1: Enable
0: Disable
PREF1 output control
1 1: Enable
0: Disable
PREF0 output control
1 1: Enable
0: Disable
1 PUSB48 output control
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Publication Release Date: Feb 2006
-8-
Revision 0.6