W83791SD Datasheet, PDF (11/22 Pages) Winbond – H/W MONITORING IC

W83791SD/W83791SG
7.4 Speech Programmable Trigger Register  Index 09h (Bank 0)
Power on default: 80h
BIT
NAME
7 TR_RDY
6:0 TRIG_REG
ATTRIBUTE
RO
R/W
DESCRIPTION
Programmable Trigger Register Ready. If return to 1, the
software or firmware can write next event to trigger register. If
return to 0, the software or firmware cannot write trigger event
to event queue, that is, the timer is not timeout yet.
Speech Programmable Trigger Register. The software or
firmware can set these bits to trigger speech sound. The
vectors of sound trigger are shown as follows. If the bit of
trigger register ready is logic 0, this trigger register will be
ignored. Therefore, the bit of the trigger ready should be read
before programming this register.
TRIG_REG<6:0>
Speech Sound Vector
00h
Vector 80h (1000_0000b) (=80h+00h)
01h
Vector 81h (1000_0001b) (=80h+01h)
02h
Vector 82h (1000_0010b) (=80h+02h)
:
:
N
Vector (80h+n)
:
:
7Eh
Vector FEh (1111_1110b) (=80h+7Eh)
7Fh
Vector FFh (1111_1111b) (=80h+7Fh)
7.5 Speech Input Trigger Property Register  Index 0Ah (Bank 0)
Power on default: 00h
BIT
NAME
ATTRIBUTE
DESCRIPTION
7 En_Program
R/W
Enable W83791SD/SG to program external serial flash
memory.
6 En_Timeout
WO
Enable Software/Firmware Trigger Timeout Function. This bit
sets the Event Trigger Timeout Function in Index 08h.
5 Busy
RO
If read this bit return “1” means SPKOUT is in busy.
4:0
EVNTRAP5-
1 Polarity
R/W
Write ‘0’ the EVNTRAP5-1 will positive edge trigger, Write ‘1’
will negative edge trigger. Default is ‘0’.
7.6 Speech Flash Memory Read Data Registers  Index 0Dh-0Eh (Bank 0)
Power on default: 00h
INDEX
NAME
0Dh SPEECHRD0
0Eh SPEECHRD1
ATTRIBUTE
RO
RO
DESCRIPTION
Speech Flash Read Data 0. Speech flash reading data
bits [7:0].
Speech Flash Read Data 1. Speech flash reading data
bits [15:8].
-8-