W29EE011 Datasheet, PDF (11/20 Pages) Winbond – 128K X 8 CMOS FLASH MEMORY

W29EE011
Read Cycle Timing Parameters
(VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
W29EE011-90
MIN. MAX.
Read Cycle Time
TRC
90
-
Chip Enable Access Time
TCE
-
90
Address Access Time
TAA
-
90
Output Enable Access Time
TOE
-
45
CE Low to Active Output
TCLZ
0
-
OE Low to Active Output
TOLZ
0
-
CE High to High-Z Output
TCHZ
-
45
OE High to High-Z Output
TOHZ
-
45
Output Hold from Address Change
TOH
0
-
W29EE011-15
MIN.
150
-
-
-
0
MAX.
-
150
150
70
-
0
-
-
45
-
45
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
WE and CE Setup Time
WE and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
WE Pulse Width
WE High Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
Byte Load Cycle Time-out
SYMBOL
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBLC
TBLCO
MIN.
-
0
50
0
0
10
10
70
70
150
50
10
0.22
300
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
10
-
-
-
-
-
-
-
-
-
-
-
200
-
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
µS
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Publication Release Date: July 1999
Revision A12