WCMA1008C1X Datasheet, PDF (6/11 Pages) Weida Semiconductor, Inc. – 128K x 8 Static RAM

Switching Waveforms
Read Cycle No.1^{[9, 10]}
ADDRESS
DATA OUT
t_RC
t_AA
t_OHA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)^{[10, 11]}
WCMA1008C1X
DATA VALID
ADDRESS
t_RC
CE₁
CE₂
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_ACE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
Notes:
8. Full Device operatin requires linear V_CC ramp from V_DR to V_CC(min) > 100 µs or stable at V_cc(min) > 100 µs.
9. Device is continuously selected. OE, CE₁ = V_IL, CE₂ = V_IH
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE₁ transition LOW and CE₂ transition HIGH.
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
I_CC
50%
I_SB
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