WCMA1008C1X Datasheet, PDF (4/11 Pages) Weida Semiconductor, Inc. – 128K x 8 Static RAM

WCMA1008C1X
Switching Characteristics^[4] Over the Operating Range
55
70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
55
70
ns
t_AA
Address to Data Valid
55
70
ns
t_OHA
Data Hold from Address
5
Change
5
ns
t_ACE
CE₁ LOW to Data Valid, CE₂
55
HIGH to Data Valid
70
ns
t_DOE
t_LZOE
t_HZOE
t_LZCE
OE LOW to Data Valid
20
35
ns
OE LOW to Low Z^[5]
0
0
ns
OE HIGH to High Z^{[5, 6]}
20
25
ns
CHEIG_{1HLOtoWLotowLZo[5}w_] Z, CE₂
5
5
ns
t_HZCE
CE₁ HIGH to
LOW to High
High Z,
Z^{[5, 6]}
CE₂
20
25
ns
t_PU
CE₁ LOW to Power-Up, CE₂
0
HIGH to Power-Up
0
ns
t_PD
CE₁ HIGH to Power-Down,
55
CE₂ LOW to Power-Down
WRITE CYCLE^[7]
70
ns
t_WC
Write Cycle Time
55
t_SCE
CE₁ LOW to Write End, CE₂
45
HIGH to Write End
70
ns
60
ns
t_AW
Address Set-Up to Write End
45
t_HA
Address Hold from Write
0
End
60
ns
0
ns
t_SA
Address Set-Up to Write
0
Start
0
ns
t_PWE
WE Pulse Width
45
50
ns
t_SD
Data Set-Up to Write End
25
30
ns
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
0
0
ns
WE HIGH to Low Z^{[5, 6]}
5
5
ns
WE LOW to High Z^[6]
20
25
ns
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I_OL/I_OH and 100-pF load capacitance.
5. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
6. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE₁ LOW and CE₂ HIGH, and WE LOW. CE₁ and WE must be LOW and CE₂ HIGH to initiate
a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
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