WCMA4016U4X Datasheet, PDF (4/12 Pages) Weida Semiconductor, Inc. – 256K x 16 Static RAM

WCMA4016U4X
AC Test Loads and Waveforms
R1
V_CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
V_CC Typ
10%
90%
R2
GND
Rise TIme: 1 V/ns
90%
10%
Fall Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
R_TH
V_TH
Parameters
R1
R2
R_TH
V_TH
3.0V
1.105
1.550
0.645
1.75V
Data Retention Characteristics (Over the Operating Range)
Parameter
V_DR
I_CCDR
t_CDR[5]
t_R[6]
Description
V_CC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions
V_CC= 1.5V
CE > V_CC – 0.2V,
V_IN > V_CC – 0.2V or V_IN < 0.2V
Unit
KOhms
KOhms
KOhms
Volts
Min.
1.5
0
t_RC
Typ.^[4]
Max.
V_ccmax
3
10
Unit
V
µA
ns
ns
Data Retention Waveform^[7]
V_CC
CE or
BHE.BLE
V_CC(min)
t_CDR
DATA RETENTION MODE
V_DR > 1.5 V
V_CC(min)
t_R
Note:
6. Full Device AC operation requires linear V_CC ramp from V_DR to V_CC(min.) > 100µs or stable at V_CC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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