WCFS0808C1E Datasheet, PDF (4/10 Pages) Weida Semiconductor, Inc. – 32K x 8 Static RAM

WCFS0808C1E
Switching Characteristics Over the Operating Range^{[3, 7]}
WCFS0808C1E 12ns
WCFS0808C1E 15ns
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
12
15
ns
t_AA
Address to Data Valid
12
15
ns
t_OHA
Data Hold from Address Change
3
3
ns
t_ACE
CE LOW to Data Valid
12
15
ns
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[8]
OE HIGH to High Z^{[8, 9]}
CE LOW to Low Z^[8]
CE HIGH to High Z^[8,9]
5
7
ns
0
0
ns
5
7
ns
3
3
ns
5
7
ns
t_PU
CE LOW to Power-Up
0
0
ns
t_PD
CE HIGH to Power-Down
WRITE CYCLE^{[10, 11]}
12
15
ns
t_WC
Write Cycle Time
12
15
ns
t_SCE
CE LOW to Write End
9
10
ns
t_AW
Address Set-Up to Write End
9
10
ns
t_HA
Address Hold from Write End
0
0
ns
t_SA
Address Set-Up to Write Start
0
0
ns
t_PWE
WE Pulse Width
8
9
ns
t_SD
Data Set-Up to Write End
8
9
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High Z^[9]
WE HIGH to Low Z^[8]
0
0
ns
7
7
ns
3
3
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels
of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I_OL/I_OH and 30-pF load capacitance.
8. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
9. t_HZOE, t_HZCE, and t_HZWE are specified with C_L = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
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