W3E232M16S-XSTX Datasheet, PDF (9/22 Pages) White Electronic Designs Corporation – 2x32Mx16bit DDR SDRAM

White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01 11
Operating Mode
DS DLL
Extended Mode
Register (Ex)
E0
DLL
0
Enable
1
Disable
E1
Drive Strength
0
Normal
1
Reduced
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2
E1, E0
Operating Mode
00000000000
Valid
Reserved
-----------
-
Reserved
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
DESELECT (NOP) (9)
NO OPERATION (NOP) (9)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
CS#
RAS#
CAS#
WE#
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
L
L
L
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
9
White Electronic Designs Corporation • [phone] • www.wedc.com