W3E232M16S-XSTX Datasheet, PDF (16/22 Pages) White Electronic Designs Corporation – 2x32Mx16bit DDR SDRAM

White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
Parameter
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQS falling edge to CK rising – setup time
DQS falling edge from CK rising – hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
CL = 2.5
CL = 2
Symbol
tAC
tCH
tCL
tCK (3)
tCK (2.5)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
t_IHF
t_ISF
t_IHs
t_ISs
tIPW
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
DDR333 CL 2.5
DDR266 CL 2
Min
-0.70
0.45
0.45
7.5
10
0.45
0.45
1.75
-0.6
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.7
0.75
0.75
0.8
0.8
2.2
12
tHP-tQHS
40
15
60
72
15
15
0.9
0.4
12
0.25
0
Max
+0.70
0.55
0.55
13
13
+0.6
0.4
1.25
+0.7
0.55
70,000
1.1
0.6
DDR266 CL 2.5
DDR200 CL 2
Unit
Min
Max
-0.70
+0.70
ns
0.45
0.55
tCK
0.45
0.55
tCK
7.5
13
ns
10
13
ns
0.5
ns
0.5
ns
1.75
ns
-0.75
+0.75
ns
0.35
tCK
0.35
tCK
0.5
ns
0.75
1.25
tCK
0.2
tCK
0.2
tCK
tCH,tCL
ns
+0.75
ns
-0.75
ns
0.90
ns
0.90
ns
1
1
2.2
ns
15
ns
tHP-tQHS
ns
0.75
ns
40
120,000
ns
20
ns
65
ns
75
ns
20
ns
20
ns
0.9
1.1
tCK
0.4
0.6
tCK
15
ns
0.25
tCK
0
ns
Notes
30
30
51
45, 51
26, 51
26, 51
31
25, 26
34
18, 42
18, 42
14
14
25, 26
35
49
43
43
20, 21
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
16
White Electronic Designs Corporation • [phone] • www.wedc.com