W3E64M72S-XBX Datasheet, PDF (8/19 Pages) White Electronic Designs Corporation – 64Mx72 DDR SDRAM

White Electronic Designs
W3E64M72S-XBX
ADVANCED
FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ^{Mode Register (Mx)}
0*
0*
Operating Mode
CAS Latency BT Burst Length
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M12 M11 M10 M9
M8
M7
M6-M0
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
Burst Starting Column
Length
Address
A0
2
0
1
A1 A0
00
4
01
10
11
A2 A1 A0
000
001
010
8
011
100
101
110
111
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1
0-1
1-0
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0
selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1
select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
Rev. 0
8
White Electronic Designs Corporation • [phone] • www.wedc.com