W3E64M72S-XBX Datasheet, PDF (14/19 Pages) White Electronic Designs Corporation – 64Mx72 DDR SDRAM

White Electronic Designs
W3E64M72S-XBX
ADVANCED
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
Notes 1-5, 14-17, 33
333 Mbs CL3/CL2.5
(53)
266 Mbs CL2.5
266 Mbs CL2.5
200 CL2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Parameter
Access window of DQs from CK/CK#
CK high-level width (30)
CK low-level width (30)
Clock cycle time
CL = 3 (45, 51)
CL = 2.5 (45, 51)
CL = 2 (45, 51)
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period (34)
Data-out high-impedance window from CK/CK# (18, 42)
Data-out low-impedance window from CK/CK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Symbol
tAC
tCH
tCL
tCK (3)
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
Min
-0.70
0.45
0.45
6
7.5
10
0.45
0.45
1.75
-0.6
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.70
0.75
0.75
0.8
0.8
12
tHP-tQHS
42
15
60
72
15
15
0.9
0.4
12
0.25
0
0.4
15
Max
+0.70
0.55
0.55
13
13
13
+0.6
0.45
1.25
+0.70
0.55
70,000
1.1
0.6
0.6
Min
Max
Min
Max
Min
Max
-0.75 +0.75
-0.8
+0.8
-0.8
+0.8
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.75
0.90
0.90
1
1
15
tHP-tQHS
40
20
65
75
20
20
0.9
0.4
15
0.25
0
0.4
15
13
13
+0.75
0.5
1.25
+0.75
0.75
120,000
1.1
0.6
0.6
8
10
0.6
0.6
2
-0.8
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
13
13
+0.8
0.6
1.25
+0.8
1
120,000
1.1
0.6
0.6
10
13
0.6
0.6
2
-0.8
0.35
0.35
0.75
0.2
0.2
tCH,tCL
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
13
15
+0.8
0.6
1.25
+0.8
1
120,000
1.1
0.6
0.6
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
Internal WRITE to READ command delay
tWTR
1
1
1
1
tCK
Data valid output window (25)
na
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
REFRESH to REFRESH command interval (23) (Commercial & Industrial only)
tREFC
70.3
70.3
70.3
70.3
µs
REFRESH to REFRESH command interval (23) (Military temperature only)*
tREFC
35
35
35
35.15
µs
Average periodic refresh interval (23) (Commercial & Industrial only)
tREFI
7.8
7.8
7.8
7.8
µs
Average periodic refresh interval (23) (Military temperature only)*
tREFI
3.9
3.9
3.9
3.9
µs
Terminating voltage delay to VDD
tVTD
0
0
0
0
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
75
80
80
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
200
200
tCK
* Self refresh available in commercial and industrial temperatures only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2005
Rev. 0
14
White Electronic Designs Corporation • [phone] • www.wedc.com