W3E16M72SR-XBX Datasheet, PDF (8/16 Pages) White Electronic Designs Corporation – 16Mx72 Registered DDR SDRAM

White Electronic Designs
W3E16M72SR-XBX
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
DESELECT (NOP) (9)
NO OPERATION (NOP) (9)
ACTIVE (Select bank and activate row) (3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
CS#
RAS#
CAS#
WE#
ADDR
H
X
X
X
X
L
H
H
H
X
L
L
H
H
Bank/Row
L
H
L
H
Bank/Col
L
H
L
L
Bank/Col
L
H
H
L
X
L
L
H
L
Code
L
L
L
H
X
L
L
L
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
DM
DQs
L
Valid
H
X
REGISTER FUNCTION TABLE
RESET#
H
H
H
L
INPUTS
RCK
↑
↑
L or H
X, or floating
RCK#
↓
↓
L or H
X, or floating
INPUT
H
L
X
X, or floating
OUTPUT
Q
H
L
Q0
L
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the D/Qs
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
February 2005
Rev. 2
8
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