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W3E16M72SR-XBX Datasheet, PDF (1/16 Pages) White Electronic Designs Corporation – 16Mx72 Registered DDR SDRAM
White Electronic Designs
W3E16M72SR-XBX
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus
speeds of 200, 225, and 250 MHz
Package:
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
Organized as 16M x 72
2.5V ±0.2V core power supply
Weight: W3E16M72SR-XBX - 2.5 grams typical
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
BENEFITS
47% SPACE SAVINGS
Glueless Connection to PCI Bridge/Memory
Controller
Reduced part count
Reduced I/O count
• 49% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
DLL to align DQ and DQS transitions with CK
Laminate interposer for optimum TCE match
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Upgradeable to 32M x 72 density (contact factory
for information)
Programmable IOL/IOH option
Auto precharge option
* This product is subject to change without notice.
Monolithic Solution
22.3
66
11.9
TSOP
11.9
11.9
22.3
66
TSOP
11.9
8.3
12.6
48
TSOP
66
22.3 TSOP
66
TSOP
66
TSOP
12.6
48
TSOP
Actual Size
S
A
V
White Electronic Designs 25 I
W3E16M72SR-XBX
N
G
32
S
Area
I/O
Count
February 2005
Rev. 2
5 x 265mm2 + 2 x 105mm2 = 1536mm2
5 x 66 pins + 2 x 48 = 426 pins
800mm2
47%
219 Balls
49%
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com