W3E16M72SR-XBX Datasheet, PDF (11/16 Pages) White Electronic Designs Corporation – 16Mx72 Registered DDR SDRAM

White Electronic Designs
W3E16M72SR-XBX
DDR DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage
I/O Supply Voltage
Input Hight Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC
Output Levels: Full drive option - x16
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option - 16 only
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage
I/O Termination Voltage
Symbol
VCC
VCCQ
VIH
VIL
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
Min
2.3
2.3
VREF + 0.15
-0.4
-2
-5
-16.8
16.8
-9
9
0.49 x VCCQ
VREF - 0.04
Max
2.7
2.7
VCC + 0.3
VREF - 0.15
2
5
–
–
–
–
0.51 x VCCQ
VREF + 0.04
Units
V
V
V
V
µA
µA
mA
mA
mA
mA
V
V
DDR ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 54)
VCC = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once
per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM (51)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50)
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
AUTO REFRESH CURRENT
tREF = tRC (MIN) (27, 50)
tREF = 7.8125µs (27, 50)
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard (11)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active READ or WRITE commands. (22, 49)
Max
250Mbps
Symbol 266Mbps 200Mbps
ICC0
625
600
ICC1
850
775
ICC2P
20
20
ICC2F
225
225
ICC3P
150
150
ICC3N
250
250
ICC4R
925
925
ICC4W
800
800
ICC5
1225
1225
ICC5A
30
30
ICC6
20
20
ICC7
2000
2000
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
February 2005
Rev. 2
11
White Electronic Designs Corporation • [phone] • www.wedc.com