W3E16M72SR-XBX Datasheet, PDF (7/16 Pages) White Electronic Designs Corporation – 16Mx72 Registered DDR SDRAM

White Electronic Designs
W3E16M72SR-XBX
FIGURE 4 – CAS LATENCY
CLK#
CLK
COMMAND
T0
READ
DQS
DQ
CLK#
CLK
COMMAND
T0
READ
DQS
DQ
T1
T2 T2n T3 T3n
NOP
CL = 2
NOP
NOP
T1
T2 T2n T3 T3n
NOP
CL = 2.5
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
TRANSITIONING DATA
DON'T CARE
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
01 11
Operating Mode
QFC# DS DLL
Extended Mode
Register (Ex)
E0
DLL
0
Enable
1
Disable
E1
Drive Strength
0
Normal
1
Reduced
E22
QFC# Function
0
Disabled
-
Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
E2, E1, E0
Operating Mode
0000000000
Valid
Reserved
----------
-
Reserved
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE# function is not supported.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automatically.)
Any time the DLL is enabled, 200 clock cycles must occur
before a READ command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
February 2005
Rev. 2
7
White Electronic Designs Corporation • [phone] • www.wedc.com