W3EG7218S-AD4 Datasheet, PDF (7/13 Pages) White Electronic Designs Corporation – 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
SYMBOL
tAC
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHS
tISS
tIPW
tMRD
262
MIN
MAX
-0.75 +0.75
0.45
0.55
0.45
0.55
7.5
13
7.5
13
0.5
0.5
1.75
-0.60 +0.75
0.35
0.35
0.5
0.75
1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
0.90
2.2
15
265/202
MIN
MAX
-0.75 +0.75
0.45
0.55
0.45
0.55
7.5
13
10
13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.6
0.75
1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
1.1
1.1
2.2
15
UNITS
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
NOTES
26
26
40, 45
40, 45
23, 27
23, 27
27
22, 23
30
16, 37
16, 37
12
12
November 2004
Rev. 1
7
White Electronic Designs Corporation • [phone] • www.wedc.com