W3EG7218S-AD4 Datasheet, PDF (10/13 Pages) White Electronic Designs Corporation – 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 8, Pull-Down Characteristics.
b. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, Pull-Down Characteristics.
c. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 9, Pull-Up Characteristics
d. The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 9, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
f. The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
35. VIH overshoot: VIH(MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a
pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
36. VCC and VCCQ must track each other.
37. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
39. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are
0Vs, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
40. The part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41. Random addressing changing and 50 percent of data changing at every transfer.
42. Random addressing changing and 100 percent of data changing at every transfer.
43. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
44. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
45. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles.
46. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
48. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
November 2004
Rev. 1
10
White Electronic Designs Corporation • [phone] • www.wedc.com