W3EG7218S-AD4 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)
DDR266
@CL=2
DDR266
@CL=2.5
Parameter
Symbol Conditions
Max
Max
Operating Current
IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS
1125
990
inputs changing once per clock cycle; Address and control
inputs changing once every two cycles. tRC=tRC(MIN); tCK=tCK
Operating Current
IDD1 One device bank; Active-Read-Precharge; Burst = 2;
1215
1080
tRC=tRC(MIN);tCK=tCK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down mode; tCK=tCK(MIN);
Down Standby Current
CKE=(low)
27
27
Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
405
405
Address and other control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-down mode; tCK(MIN);
CKE=(low)
225
225
Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;
450
450
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; tCK=tCK(MIN); IOUT = 0mA.
1260
1170
Operating Current
IDD4W Burst = 2; Writes; Continous burst; One device bank active;
1260
1125
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
Auto Refresh Current IDD5 tRC=tRC(MIN)
2385
1980
Self Refresh Current
IDD6 CKE ≤ 0.2V
27
27
Operating Current
IDD7A Four bank interleaving Reads (BL=4) with auto precharge with
3195
2970
tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change
only during Active Read or Write commands
DDR200
@CL=2
Max
990
1080
27
405
225
450
1170
1125
1980
27
2970
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
November 2004
Rev. 1
5
White Electronic Designs Corporation • [phone] • www.wedc.com