W3E16M64S-XBX Datasheet, PDF (6/16 Pages) White Electronic Designs Corporation – 16Mx64 DDR SDRAM

White Electronic Designs
W3E16M64S-XBX
FIGURE 3 – MODE REGISTER DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0*
0*
Operating Mode
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
CAS Latency BT Burst Length
Mode Register (Mx)
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M12 M11 M10 M9
M8
M7
M6-M0
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
TABLE 1 – BURST DEFINITION
Burst
Length
2
4
8
Starting Column
Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
000
001
010
011
100
101
110
111
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1
0-1
1-0
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC#. These functions are controlled via the bits
shown in Figure 5. The extended mode register is
programmed via the LOAD MODE REGISTER command
to the mode register (with BA0 = 1 and BA1 = 0) and
will retain the stored information until it is programmed
again or the device loses power. The enabling of the DLL
should always be followed by a LOAD MODE REGISTER
command to the mode register (BA0/BA1 both LOW) to
reset the DLL.
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
February 2005
Rev. 4
6
White Electronic Designs Corporation • [phone] • www.wedc.com