W3E16M64S-XBX Datasheet, PDF (11/16 Pages) White Electronic Designs Corporation – 16Mx64 DDR SDRAM

White Electronic Designs
W3E16M64S-XBX
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +2.5V ±0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Min
Max
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC
Output Levels: Full drive option
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage
I/O Termination Voltage
VCC
VCCQ
VIH
VIL
II
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
2.3
2.3
VREF - 0.04
-0.3
-2
-8
-5
-12
12
2.7
2.7
VREF + 0.04
VREF - 0.15
2
8
5
—
—
-9
—
9
—
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
Units
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
V
V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14)
VCC = +2.5V ±0.2V; -55°C ≤ TA ≤ +125°C
Max
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE =
LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW
(23, 32, 50)
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once
per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
AUTO REFRESH CURRENT
tRC = tRC (MIN) (27, 50)
tRC = 7.8125µs (27, 50)
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard (11)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK
(MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49)
250Mbps
Symbol 266Mbps 200Mbps
ICC0
500
480
ICC1
680
620
ICC2P
16
16
ICC2F
180
180
ICC3P
120
120
ICC3N
200
200
ICC4R
740
740
ICC4W
640
640
ICC5
980
980
ICC5A
24
24
ICC6
16
16
ICC7 1600 1600
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
February 2005
Rev. 4
11
White Electronic Designs Corporation • [phone] • www.wedc.com