W3E32M72S-XSBX Datasheet, PDF (4/19 Pages) White Electronic Designs Corporation – 32Mx72 DDR SDRAM

White Electronic Designs
W3E32M72S-XSBX
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
VREF
A0-12
BA0-1
CK0
CK0#
CKE0
CS0#
DQML0
DQMH0
DQSL0
DQSH0
WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK# _U0
CKE
CS#
DQML
DQMH
DQSL
DQSH
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
CK1
CK1#
CKE1
CS1#
DQML1
DQMH1
DQSL1
DQSH1
WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK# _U1
CKE
CS#
DQML
DQMH
DQSL
DQSH
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
CK2#
CK2#
CKE2
CS2#
DQML2
DQMH2
DQSL2
DQSH2
WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK# _U2
CKE
CS#
DQML
DQMH
DQSL
DQSH
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
CK3
CK3#
CKE3
CS3#
DQML3
DQMH3
DQSL3
DQSH3
WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK# _U3
CKE
CS#
DQML
DQMH
DQSL
DQSH
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
CK4
CK4#
CKE4
CS4#
DQML4
DQMH4
DQSL4
DQSH4
WE# RAS# CAS#
VREF
A0-12
BA0-1
CK
CK# _U4
CKE
CS#
DQML
DQMH
DQSL
DQSH
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
WE0#
RAS 0#
CAS0#
DQ0
=Y
=Y
=Y
=Y
=Y
=Y
DQ15
WE1#
RAS 1#
CAS1#
DQ16
=Y
=Y
=Y
=Y
=Y
=Y
DQ31
WE2#
RAS2#
CAS2#
DQ32
=Y
=Y
=Y
=Y
=Y
=Y
DQ47
WE3#
RAS3#
CAS3#
DQ48
=Y
=Y
=Y
=Y
=Y
=Y
DQ63
WE4#
RAS4#
CAS4#
DQ64
=Y
=Y
=Y
=Y
=Y
=Y
DQ79
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after VCC is
applied. After CKE passes through VIH, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
4
White Electronic Designs Corporation • [phone] • www.wedc.com