W332M72V-XSBX Datasheet, PDF (12/15 Pages) White Electronic Designs Corporation – 32Mx72 Synchronous DRAM

White Electronic Designs
W332M72V-XSBX
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition
Symbol
-100
-125
-133
READ/WRITE command to READ/WRITE command (17)
tCCD
1
1
1
CKE to clock disable or power-down entry mode (14)
tCKED
1
1
1
CKE to clock enable or power-down exit setup mode (14)
tPED
1
1
1
DQM to input data delay (17)
tDQD
0
0
0
DQM to data mask during WRITEs
tDQM
0
0
0
DQM to data high-impedance during READs
tDQZ
2
2
2
WRITE command to input data delay (17)
tDWD
0
0
0
Data-in to ACTIVE command (15)
tDAL
4
5
5
Data-in to PRECHARGE command (16)
tDPL
2
2
2
Last data-in to burst STOP command (17)
tBDL
1
1
1
Last data-in to new READ/WRITE command (17)
tCDL
1
1
1
Last data-in to PRECHARGE command (16)
tRDL
2
2
2
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
tMRD
2
2
2
Data-out to high-impedance from PRECHARGE command (17)
CL = 3
tROH
3
3
3
CL = 2
tROH
2
—
—
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. ICC is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously.) The two AUTO REFRESH command wake-
ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid VIH or VIL levels.
13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact
that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
22. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
Ju;y 2006
Rev. 3
12
White Electronic Designs Corporation • [phone] • www.wedc.com