W332M72V-XSBX Datasheet, PDF (11/15 Pages) White Electronic Designs Corporation – 32Mx72 Synchronous DRAM

White Electronic Designs
W332M72V-XSBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
-100
-125
-133
Symbol
Min
Max
Min
Max
Min
Max
Unit
Access time from CLK (pos.
CL = 3
tAC
7
edge)
CL = 2
tAC
7
6
5.5
ns
6
6
ns
Address hold time
tAH
1
1
0.8
ns
Address setup time
tAS
2
2
1.5
ns
CLK high-level width
tCH
3
3
2.5
ns
CLK low-level width
tCL
3
3
2.5
ns
CL = 3
tCK
10
8
7.5
ns
Clock cycle time (22)
CL = 2
tCK
13
10
10
ns
CKE hold time
tCKH
1
1
0.8
ns
CKE setup time
tCKS
2
2
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
1
0.8
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
2
2
1.5
ns
Data-in hold time
tDH
1
1
0.8
ns
Data-in setup time
tDS
2
2
1.5
ns
CL = 3 (10)
tHZ
7
Data-out high-impedance time
CL = 2 (10)
tHZ
7
6
5.5
ns
6
6
ns
Data-out low-impedance time
tLZ
1
1
1
ns
Data-out hold time (load)
tOH
3
3
3
ns
Data-out hold time (no load) (26)
tOHN
1.8
1.8
1.8
ns
ACTIVE to PRECHARGE command
tRAS
50
120,000
50
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
tRC
70
68
68
ns
ACTIVE to READ or WRITE delay
tRCD
20
20
20
ns
Refresh period (8,192 rows) – Commercial,
tREF
64
64
64
ms
Industrial
Refresh period (8,192 rows) – Military
tREF
16
16
16
ms
AUTO REFRESH period
tRFC
70
70
70
ns
PRECHARGE command period
tRP
20
20
20
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
20
20
20
ns
Transition time (7)
tT
0.3
1.2
0.3
1.2
0.3
1.2
ns
(23)
1 CLK + 7ns
1 CLK + 7ns
1 CLK +
—
WRITE recovery time
tWR
7.5ns
(24)
15
15
15
ns
Exit SELF REFRESH to ACTIVE command
tXSR
80
80
75
ns
Ju;y 2006
Rev. 3
11
White Electronic Designs Corporation • [phone] • www.wedc.com