VSC7135 Datasheet, PDF (6/16 Pages) Vitesse Semiconductor Corporation – 1.25Gbits/sec Gigabit Ethernet Transceiver

VITESSE
SEMICONDUCTOR CORPORATION
1.25Gbits/sec
Gigabit Ethernet Transceiver
RCLK
Figure 5: Receive Timing Waveforms
T₄
T₃
Data Sheet
VSC7135
RCLKN
R0:9
Data Valid
T₁
T₂
Data Valid
Data Valid
Table 2: Receive AC Characteristics
Parameters
T₁
T₂
T₃
T₄
Description
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
Data or COM_DET Valid
after RCLK or RCLKN
rise
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
delay=
-^f---^b---^a--^u---^d-
10
±
T₃
Deviation of RCLK,
RCLKN frequency from
nominal.
f _RCLK=
-^f---^R---^E----^F---^C---^L---^K--
2
±
T₄
Min.
3.0
2.0
-500
-1.0
Max. Units
Conditions
—
ns. _{Measured between the 1.4V}
point of RCLK or RCLKN
and a valid level of R0:9. All
—
ns. ^{outputs driving 10pF load.}
500
ps.
Nominal delay is 10 bit times.
Tested on sample basis
Whether or not locked to
1.0
% _{serial data}
T_R, T_F
R_lat
T_LOCK
T_jtd
D_jtd
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
—
2.4
ns.
Between V_il(max) and V_ih(min),
into 10 pf. load.
Latency from RX to R0:9 15bc + 2ns 34bc + 2ns
bc = Bit clock
ns = Nano second
Data acquisition lock time
@ 1.25 Gb/s
—
2.0
µs.
8B/10B IDLE pattern.
Tested on a sample basis
Total receive data jitter
tolerance (p-p)
599
ps
IEEE 802.3Z Clause 38.68,
tested on a sample basis
Total deterministic data
jitter tolerance (p-p)
370
ps
IEEE 802.3Z Clause 38.69,
tested on a sample basis
NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52146-0, Rev. 4.0
5/28/98