SI9122E Datasheet, PDF (9/20 Pages) Vishay Siliconix – 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

The soft-start circuit is designed for the dc-dc converter to
start-up in an orderly manner and reduce component
stresses on the Converter. This feature is programmable by
selecting an external C_SS. An internal 20 µA current source
charges C_SS from 0 V to the final clamped voltage of 8 V. In
the event of UVLO or shutdown, V_SS will be held low (< 1 V)
disabling driver switching. To prevent oscillations, a longer
soft-start time may be needed for highly capacitive loads
and/or high peak output current applications.
Reference
The reference voltage of Si9122E is set at 3.3 V. The
reference voltage should be de-coupled externally with
0.1 µF capacitor. The V_REF voltage is 0 V in shutdown mode
and has 50 mA source capability.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage
mode and generates a fixed frequency pulse width
modulated signal to the drivers. Duty cycle is controlled over
a wide range to maintain output voltage under line and load
variation. Voltage feedforward is also included to take
account of variations in supply voltage V_IN.
In the half-bridge topology requiring isolation between output
and input, the reference voltage and error amplifier must be
supplied externally, usually on the secondary side. The error
information is thus passed to the power controller through an
opto-coupling device. This information is inverted, hence 0 V
represents the maximum duty cycle, while 2 V represents
minimum duty cycle. The error information enters the IC via
pin EP, and is passed to the PWM generator via an inverting
amplifier. The relationship between Duty cycle and V_EP is
shown in the Typical Characteristic Graph, Duty Cycle vs.
V_EP 25 °C , page 12. Voltage feedforward is implemented by
taking the attenuated V_IN signal at V_INDET and directly
modulating the duty cycle.
At start-up, i.e., once V_CC is greater than V_UVLO, switching is
initiated under soft-start control which increases primary
switch on-times linearly from D_MIN to D_MAX over the soft-start
period. Start-up from a V_INDET power down is also initiated
under soft-start control.
Half Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122E controls the
low and high-side bridge drivers on alternative cycles. A
period of inactivity always results after initiation of the soft-
start cycle until the soft-start voltage reaches approximately
1.2 V and PWM controlled switching begins. The first bridge
driver to switch is always the low-side (DL), as this allows
charging of the high-side boost capacitor.
The timing and coordination of the drives to the primary and
secondary stages is very important and shown in figure 3. It
is essential to avoid the situation where both of the
secondary MOSFETs are on when either the high or the low-
side switch are active. In this situation the transformer would
effectively be presented with a short across the output. To
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Si9122E
Vishay Siliconix
avoid this, a dedicated break-before-make circuit is included
which will generate non-overlapping waveforms for the
primary and the secondary drive signals. This is achieved by
a programmable timer which delays the on switching of the
primary driver relative to the off switching of the related
secondary and subsequently delays the on switching of the
secondary relative to the off switching of the related primary.
Typical variations of BBM times with respect to R_BBM and
other operating parameters are shown on page 14 and 15.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is
provided directly from V_CC. The high-side MOSFET however
requires the gate voltage to be enhanced above V_IN. This is
achieved by bootstrapping the V_CC voltage onto the LX
voltage (the high-side MOSFET source). In order to provide
the bootstrapping an external diode and capacitor are
required as shown on the application schematic. The
capacitor will charge up after the low-side driver has turned
on. The switch gatedrive signals DH and DL are shown in
figure 3.
Secondary MOSFET Drivers
The secondary side MOSFETs are driven from the Si9122E
via a center tapped pulse transformer and inverter drivers.
The waveforms from SR_H and SR_L are shown in figure 3. Of
importance is the relative voltage between SR_H and SR_L, i.e.
that which is presented across the primary of the pulse
transformer. When both potentials of SR_L and SR_H are equal
then by the action of the inverting drivers both secondary
MOSFETs are turned on.
Oscillator
The oscillator is designed to operate at a nominal frequency
of 500 kHz. The 500 kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by
attaching a resistor to the R_OSC pin. Under overload
conditions the oscillator frequency is reduced by the current
overload protection to enable a constant current to be
maintained into a low impedance circuit.
Current Limit
Current mode control providing constant current operation is
achieved by monitoring the differential voltage V_CS between
the CS1 and CS2 pins, which are connected to a current
sense resistor on the primary low-side MOSFET. In the
absence of an overcurrent condition, V_CS is less than lower
current limit threshold V_TLCL (typical 100 mV); C_{L_CONT} is
pulled up linearly via the 120 µA current source (I_PU) and
both DL and DH switch at half the oscillator set frequency.
When a moderate overcurrent condition occurs (V_TLCL < V_CS
< V_THCL), the C_{L_CONT} capacitor will be discharged at a rate
that is proportional to V_CS - 100 mV by the I_PD current
source. Both driver outputs are in frequency fold-back mode
and the switching frequency becomes roughly 20 % of
www.vishay.com
9