SI9122E Datasheet, PDF (5/20 Pages) Vishay Siliconix – 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Si9122E
Vishay Siliconix
SPECIFICATIONS^a
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
f_NOM = 500 kHz, V_IN = 75 V
V_INDET = 7.5 V; 10.5 V ≤ V_CC ≤ 13.2 V
Limits
- 40 to 85 °C
Min.^b
Typ.^c
Max.^b
Converter Supply Current (V_CC)
Shutdown
I_CC1
Shutdown, V_INDET = 0 V
50
350
Converter Supply Current (V_CC)
Switching Disabled
I_CC2
Switching w/o Load
I_CC3
Switching with C_LOAD
I_CC4
V_INDET < V_REF
V_INDET > V_REF, f_NOM = 500 kHZ
V_CC = 12 V, C_DH = C_DL = 3 nF
C_SRH = C_SRL = 0.3 nF
4
8
12
5
10
15
21
Output MOSFET DH Driver (High-Side)
Output High Voltage
Output Low Voltage
Boost Current
LX Current
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
V_OH
V_OL
I_BST
I_LX
I_SOURCE
I_SINK
t_r
t_f
Sourcing 10 mA
Sinking 10 mA
V_LX = 48 V, V_BST = V_LX + V_CC
V_LX = 48 V, V_BST = V_LX + V_CC
V_CC = 10.5 V
C_DH = 3 nF
V_BST - 0.3
1.3
- 1.3
0.75
1.9
- 0.7
- 1.0
1.0
35
35
V_LX + 0.3
2.7
- 0.4
- 0.75
Output MOSFET DL Driver (Low-Side)
Output High Voltage
Output Low Voltage
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
V_OH
V_OL
I_SOURCE
I_SINK
t_r
t_f
Sourcing 10 mA
Sinking 10 mA
V_CC = 10.5 V
C_DH = 3 nF
V_CC - 0.3
- 1.0
0.75
1.0
35
35
0.3
- 0.75
Synchronous Rectifier (SR_H, SR_L) Drivers
Output High Voltage
V_OH
Sourcing 10 mA
V_CC - 0.4
Output Low Voltage
V_OL
Sinking 10 mA
0.4
t_BBM1
T_A = 25 °C, R_BBM = 33 kΩ, V_INDET = 4.8 V,
48
Break-Before-Make Time^e
t_BBM2
t_BBM3
V_EP = 0 V, V_IN = 48 V
T_A = 25 °C, R_BBM = 33 kΩ, BST= 60 V,
9
24
t_BBM4
V_INDET = 4.8 V, V_EP = 0 V, V_IN = 48 V = LX
18
Peak Output Source
Peak Output Sink
I_SOURCE
I_SINK
V_CC = 10.5 V
- 100
100
Rise Time
Fall Time
t_r
t_f
C_DH = 3 nF
35
35
Voltage Mode
Error Amplifier
t_d1DH
t_d2DL
Input to High-Side Switch Off
Input to Low-Side Switch Off
< 200
< 200
Current Mode
Current Amplifier
t_d3DH
t_d4DL
Input to High-Side Switch Off
Input to Low-Side Switch Off
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
< 200
< 200
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. F_MIN when VC_{L_CONT} at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature.
e. See Figure 3 for Break-Before-Make time definition.
f. V_UVLO tracks V_REG1 by a diode drop.
g. Guaranteed by design and characterization, not tested in production.
Unit
µA
mA
V
mA
A
ns
V
A
ns
V
ns
mA
ns
ns
ns
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
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