SI9122E Datasheet, PDF (11/20 Pages) Vishay Siliconix – 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

REDUCTION OF BBM_{2, 4} AT HIGHER f_OSC
The start of a switching period is defined as the turning point
of the oscillator, marked in Figure 7 as A, with the end of a
switching period marked as B. For a half bridge, two
switching periods are required for both the primary high-side
and low-side drivers to operate as shown in Figure 3. For a
given oscillator frequency there is a finite time in which all
events from equation (1) have to occur. These are t_dt dead-
time duration which is a function of V_EP, t_pd1 is the
propagation delay from the PWM to SR_L (or SR_H ) output
going low, t_BBM1 (or t_BBM3) rise delay, DL (or DH) primary
driver on-time, t_pd2 is the propagation delay from PWM to DL
(or DH) output going low and t_BBM2(or t_BBM4) fall delay.
Figure 7 shows the switching cycle for the low side primary
driver and associated synchronous driver and equation (1)
shows the switching time components.
At 500 kHz and maximum duty t_pd2 is typically 60 ns.
T_switch = 1/2t_dt + t_pd1+ t_SRLOFF + 1/2t_dt - t_pd2- t_BBM2 (1)
A
B
MAX
V EP
1.2 V
½ deadtime
½ deadtime
SR _L
Tpd1
Tpd2
DL
BBM1
BBM2
Transition
point
Figure 7. Components of a Low-Side Switching Period
The Si9122E has an improved primary and secondary duty
cycles with typical maximum secondary duty at 93.2 %.
Hence the dead-time is 6.8 % or 136 ns at 500 kHz. Half of
the dead-time is 68 ns and during this time t_pd2 plus t_BBM2
has to occur before the next transition point of the oscillator
cycle. R_BBM contributes 1.2 ns/kΩ to t_BBM2; with 33 kΩ this
amounts to 40 ns. If t_BBM2 is set beyond the transition point,
SR_L will be forced high due to logic conditions and a
reduction in the set t_BBM2 will be determined by the half dead-
time minus t_pd2 and will be independent of the R_BBM value as
shown in figure 8.
Note: this applies to t_BBM4 as well.
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Si9122E
Vishay Siliconix
To mitigate the decrease in set t_BBM2 and t_BBM4, the
following criteria must be met. The set t_BBM2 plus its
associated t_pd2 must not exceed 3.4 % of the oscillator
period. The typical t_BBM2 and t_BBM4 delays are provided in
figure 9 to facilitate setting these delays for a given frequency
with R_BBM of 33 kΩ.
t_BBM2 + t_pd2 < 3.4 % of oscillator period
(2)
t_BBM4 + t_pd4 < 3.4 % of oscillator period
(3)
It is critical to avoid the condition where the sum of t_BBM2(set)
and t_pd2 is greater than 6.8 % of oscillator period whereby the
correct sequence of logic signals cannot be guaranteed.
A
B
1.2 V
SR _L
Tpd1
DL
BBM1
Actual
BBM2
Tpd2
Set BBM2
Transition
point
Figure 8. Components of a Low-Side Switching Period with
Maximum Duty and Limited BBM2
60
BBM4
50
40
30
BBM2
20
10
0
150 200 250 300 350 400 450 500
Fosc (kHz)
Figure 9. Reduction in BBM2 and BBM4
Si9122E BBM vs. F_OSC, V_IN = 50 V, V_CC = 10 V,
BST = 60 V, LX = 50 V, V_EP = 0 V
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