SI8457DB Datasheet, PDF (7/11 Pages) Vishay Siliconix – P-Channel 12 V (D-S) MOSFET

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Package Information
Vishay Siliconix
MICRO FOOT^®: 4-Bumps
(1.6 mm x 1.6 mm, 0.8 mm Pitch, 0.290 mm Bump Height)
Mark on backside of die
XXXX
XXX
b1
Note 5
4x Ø b1
D
D
S
G
S
e
S
D
b
K
4x 0.30 to .31
(Note 3)
Solder mask-0.4
e
Recommended land pattern
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
DIM.
A
A1
A2
b
b1
e
s
D
E
K
MIN.
0.550
0.260
0.290
0.370
0.360
1.520
1.520
0.155
MILLIMETERS
NOM.
0.575
0.275
0.300
0.390
0.300
0.800
0.380
1.560
1.560
0.185
Note
• Use millimeters as the primary measurement.
MAX.
0.600
0.290
0.310
0.410
0.400
1.600
1.600
0.215
MIN.
0.0217
0.0102
0.0114
0.0146
0.0141
0.0598
0.0598
0.0061
INCHES
NOM.
0.0226
0.0108
0.0118
0.0153
0.0118
0.0314
0.0150
0.0614
0.0614
0.0073
MAX.
0.0236
0.0114
0.0122
0.0161
0.0157
0.0630
0.0630
0.0085
ECN: T15-0175-Rev. A, 27-Apr-15
DWG: 6038
Revision: 27-Apr-15
1
Document Number: 69378
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000