SI9750 Datasheet, PDF (6/9 Pages) Vishay Siliconix – In-Rush Current Limit MOSFET Driver

Si9750
Vishay Siliconix
di/dt Limiting On Hot and Cold Insertion (GATE pin)
The GATE pin provides a constant current source that is used
to control the rate of rise of the gate of the MOSFET, and
hence to control the di/dt of the load and source current. The
equation that governs the gate current is:
I_SOURCE
=
1.25
V
×
-----¹---²-------
R_BIAS
=
12 m A
(4)
(for R_BIAS = 12.5kΩ)
Typically, a 33-nF capacitor should be connected from the
GATE pin to ground. If a large I_SOURCE is needed for high di/
dt, a 330-Ω resistor in series with C_GATE may be necessary to
prevent oscillation. In the case that V_DD > 6 V, a resistor of
approximately 330 Ω is also recommended in series with the
gate (Figure 1).
Reference Bias Current
(R_BIAS pin)
This pin sets the internal current used by R_LIMSET to
determine all the current limit points. Typically R_BIAS =
12.5 kΩ which sets a 20-µA bias current. The equation which
relates R_BIAS to I_BIAS is:
I_BIAS
=
-----¹---^.--²---⁵----^V-------
5 × R_BIAS
=
20 µ A
(5)
(for R_BIAS = 12.5kΩ)
Logic Control
(STATUS, ENABLE, RESET, V_RST and C_RST pins)
STATUS. The status monitor detects when the load voltage is
90% of input voltage, V_LOAD > 0.9 x V_DD. This pin is an open-
drain NMOS output, capable of sinking 200 µA at V_OL = 0.4 V.
If this pin is used in conjunction with the ENABLE of another
unit, power supply sequencing (or daisy-chaining) is easily
implemented.
ENABLE. This CMOS logic compatible input serves as the
on/off control pin. This pin has 40-µA minimum pull-up to
V_DD.
RESET (V_RST, C_RST, RESET pins). This is a standard
implementation of the microprocessor reset function. A
comparator looks at the voltage on V_RST pin and compares it
with 1.25 V. This function is programmable by using an
external voltage divider. When V_RST is higher than 1.25 V, the
reset signal is delayed by the C_RST pin, defined by Equation
(6) and then goes high (Figure 8).
Reset delay t_RSTD ≈ 10⁴ × C_RST
(6)
Power on Reset (POR)
(V_DD pin)
This function monitors the voltage on the V_DD pin and signals
the system if all input voltage requirements have been met. At
turn-on when V_DD > 2.7 V " 200 mV, a POR signal is
generated for a duration of 100 µs. After this point the system
is released into operation. If V_DD falls below 2.7 V " 200 mV, a
second POR signal will be generated. If two POR signals are
detected, this indicates that the source for V_DD is not capable
of supplying the load current. The IC then turns off the
MOSFET and initiates its retry period, hence fully protecting
the MOSFET from an over-power condition.
Boost Converter
(COIL, BOOST pins)
The boost converter generates the gate drive for the external
n-channel MOSFET. This is limited to typically V_DD + 11 V.
The boost inductor should typically be 100 µH, <3.5 Ω,
>180 mA dc, and the boost capacitor should be 100 nF.
FIGURE 2. Typical Operation Under Start-up Condition with
an Overcurrent Fault Applied to the Output
S-60752—Rev. C, 05-Apr-99
6
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