IRF820 Datasheet, PDF (5/8 Pages) Motorola, Inc – N-CHANNEL Enhancement-Mode Silicon Gate TMOS

Fig. 9 - Maximum Drain Current vs. Case Temperature
IRF820, SiHF820
Vishay Siliconix
V_DS
V_GS
R_G
R_D
D.U.T.
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
+_{- VDD}
Fig. 10a - Switching Time Test Circuit
V_DS
90 %
10 %
V_GS
t_d(on) t_r
t_d(off) t_f
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V_DS
Vary t_p to obtain
required I_AS
R_G
10 V
t_p
L
D.U.T.
I_AS
0.01 Ω
+
- ^VDD
Fig. 12a - Unclamped Inductive Test Circuit
V_DS
V_DS
t_p
V_DD
I_AS
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91059
S-81276-Rev. A, 16-Jun-08
www.vishay.com
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