SI5448DU Datasheet, PDF (1/7 Pages) Vishay Siliconix – N-Channel 40 V (D-S) MOSFET

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Si5448DU
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
PowerPAK^® ChipFET^® Single
D
S
D
6
D
7
8
5
1 _3.0 ^mm
Top View
1
S
9
4
3
D
2
D
D
G
Bottom View
FEATURES
• TrenchFET^® Gen IV power MOSFET
• 100 % R_g and UIS tested
• Thermally enhanced PowerPAK ChipFET package
-Compact footprint area - less than 6.09 mm²
-Thin 0.8 mm profile
• 56 % lower R_DS(ON) than the prior generation
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
PRODUCT SUMMARY
V_DS (V)
R_DS(on) max. () at V_GS = 10 V
R_DS(on) max. () at V_GS = 4.5 V
Q_g typ. (nC)
I_D (A) ^{a, g}
Configuration
40
0.00775
0.00947
12.6
25
Single
APPLICATIONS
D
• DC/DC converters
• Motor drive control
• Synchronous rectification
G
• Battery management
• Load switch
N-Channel MOSFET
S
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
PowerPAK ChipFET
Si5448DU-T1-GE3
ABSOLUTE MAXIMUM RATINGS (T_A = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-source voltage
Gate-source voltage
Continuous drain current (T_J = 150 °C)
Pulsed drain current (t = 100 μs)
T_C = 25 °C
T_C = 70 °C
T_A = 25 °C
T_A = 70 °C
Continuous source-drain diode current
Single pulse avalanche current
Single pulse avalanche energy
T_C = 25 °C
T_A = 25 °C
L = 0.1 mH
T_C = 25 °C
Maximum power dissipation
T_C = 70 °C
T_A = 25 °C
T_A = 70 °C
Operating junction and storage temperature range
Soldering recommendations (peak temperature) ^{d, e}
V_DS
V_GS
I_D
I_DM
I_S
I_AS
E_AS
P_D
T_J, T_stg
LIMIT
40
+20 / -16
25 ^a
25 ^a
15.9 ^{b, c}
12.7 ^{b, c}
100
25 ^a
2.6 ^{b, c}
15
11.25
31
20
3.1 ^{b, c}
2 ^{b, c}
-55 to +150
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYPICAL
MAXIMUM
UNIT
Maximum junction-to-ambient ^{b, f}
t  10 s
R_thJA
34
Maximum junction-to-case (drain)
Steady state
R_thJC
4
40
4
°C/W
Notes
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 90 °C/W.
g. T_C = 25 °C.
S16-2343-Rev. A, 14-Nov-16
1
Document Number: 76149
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000