PRM48BF480T500A00 Datasheet, PDF (40/45 Pages) Vicor Corporation – PRM™ Regulator

PRM48B x 480 y 500A00
Note that during the bursts of switching, the powertrain
frequency is constant, but the number of pulses as well as the
time between bursts is variable. The variability depends on
many factors including input voltage, output voltages, load
impedance, and error amplifier output impedance.
In burst mode, the gain of the SHARE/CONTROL NODE input
to the plant which is modeled in the previous sections is time
varying. Therefore the small signal analysis cannot be directly
applied to burst mode operation.
Input and Output filter design
Figures 14 and 15 provide the total input and output charge
per cycle, as well as switching frequency, of the PRM at full
load under various input and output voltages conditions.
Figure 13 provides the effective internal capacitance of the
module. A conservative estimate of input and output peak-
peak voltage ripple at nominal line and trim is provided by
equation (12):
V

Q_TOT

I_FL  0.4
f _SW
(12)
C_INT  C_EXT
Q_TOT is the total input (Fig. 14) or output (Fig. 15) charge per
switching cycle at full load, while C_INT is the module internal
effective capacitance at the considered voltage (Fig. 13) and
C_EXT is the external effective capacitance at the considered
voltage.
Input filter stability
The PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply
source as well as the interconnecting line are stable and do not
oscillate. For this purpose, the converter dynamic input
impedance magnitude r_{EQ _ IN} is provided in Figures 21, 22,
23. It is recommended to provide adequate design margin with
respect to the stability conditions illustrated in the previous
sections.
Inductive source and local, external input decoupling
capacitance with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series
R_LINE L_LINE circuit. The high performance ceramic decoupling
capacitors will not significantly damp the network because of
their low ESR; therefore in order to guarantee stability the
following conditions must be verified:
R_line

(C_{IN _ INT}
L_line
 C_{IN _ EXT} ) 
r_{EQ _ IN}
(13)
R_line  r_{EQ _ IN}
(14)
It is critical that the line source impedance be at least an
octave lower than the converter’s dynamic input resistance
(14). However, R_LINE cannot be made arbitrarily low otherwise
equation (13) is violated and the system will show instability,
due to under-damped RLC input network.
Inductive source and local, external input decoupling
capacitance with significant R_{CIN_EXT} ESR (i.e.: electrolytic
type)
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor L_LINE. Notice
that, the high performance ceramic capacitors C_{IN_INT} within the
PRM should be included in the external electrolytic
capacitance value for this purpose. The stability criteria will be
r  R _{EQ _ IN}
C _{IN _ EXT}
(15)
L_line
C  R ^{ r} _{IN _ EXT}
C _{IN _ EXT}
EQ _ IN
(16)
Equation (16) shows that if the aggregate ESR is too small –
for example by using very high quality input capacitors
(C_{IN_EXT}) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying (15) should be considered the minimum.
Layout Considerations
Application Note AN:005 details board layout
recommendations using V•I Chip components, with details on
good power connections, reducing EMI, and shielding of
control signals and techniques to reference them to SGND.
Avoid routing control signals (ENABLE, TRIM, AL etc.) directly
underneath the PRM. It is critical that all control signals (aside
from VC and VT) are referenced to SGND, both for routing and
for pull-down and bypassing purposes. VC and VT provide
control and feedback from a VTM, and must be referenced to
–OUT of the PRM (-IN of the VTM)
SGND is connected to –IN internally to the PRM. SGND
should not be tied to any other ground in the system.
- 40 -
Rev. 1.0
11/2012