PRM48BF480T500A00 Datasheet, PDF (33/45 Pages) Vicor Corporation – PRM™ Regulator

PRM48B x 480 y 500A00
Arrays (Adaptive Loop / Slave operation)
In Adaptive Loop operation a master-slave configuration is
used for arrays. Up to 5 PRMs of the same type may be
placed in parallel to expand the power capacity of the system.
One PRM is designated as the master and contains the active
control loop which considers control pin inputs and drives
SHARE. The other PRMs listen to SHARE and act as slave
powertrains only. The following high-level guidelines must be
followed in order for the resultant system to start up and
operate properly, and to avoid overstress or exceeding any
absolute maximum ratings.
 One PRM must be designated as a master through
configuring the TRIM pin voltage within the
recommended range.
 All other PRMs must be designated as slave PRMs by
tying TRIM pins to SGND. It is recommended to make
this connection through a 0Ω jumper for
troubleshooting purposes.
 All PRMs in the array must be powered from a
common power source so that the input voltage to
each PRM is the same. The IN pins of all PRMs must
be connected together.
 An independent fuse for each PRM +IN connection is
required to maintain safety certifications (see Fusing
section).
 An independent inductor for each PRM +IN connection
is recommended when used in an array, to control
circulating currents among the PRM inputs and reduce
the impact of beat frequencies.
 Mismatches in both inductance, and resistance from
the common power source to each PRM should be
minimized.
 ENABLE pins must be connected together for start up
synchronization and proper fault response of the array.
 SHARE pins must be connected together to enable
sharing. The bandwidth requirements of SHARE are
low enough that the bus can be considered a lumped
element, rather than a transmission line, and so star
connections to the master PRM with stubs, as well as
daisy chain connections are permitted.
 The resistances between slave unit SHARE pins and
the master’s should be well matched, to avoid
introducing additional sharing mismatches. The
SHARE bus should not be routed under any PRM.
SHARE bus parasitic capacitance to +IN or +OUT
should be minimized.
 SGND of the master PRM is the reference for all
control loop functions. The SGND pins of each slave
PRMs should be connected to the SGND reference
node on the board through a 1 Ω resistor.
 When operating within an array, the master PRM is
rated for full power while the slave PRMs are de-rated
to the array rated power and current values provided
for Slave operation(P_{OUT_ARRAY},I_{OUT_ARRAY}). The
number of PRMs required to achieve a given array
capacity must consider these de-ratings to avoid
overstressing any PRM in the array.
 Adaptive Loop design procedures above will hold for
an array, in general, although some parameters must
be scaled against the number of PRMs in the system.
Arrays of more than 5 PRMs may be possible through use of
external circuitry. Please contact Vicor Applications for
assistance with array sizing above 5 units.
- 33 -
Rev. 1.0
11/2012