PRM48BF480T500A00 Datasheet, PDF (39/45 Pages) Vicor Corporation – PRM™ Regulator

PRM48B x 480 y 500A00
DESIGN GUIDELINES (General Operation)
The following guidelines are general guidelines that apply to
any mode of operation.
Vout
k
d
Vout
k
d
FPA System Considerations
Iout
time
Iout
time
There are a few system level design considerations that should
be carefully considered when using a PRM and VTM to
implement a Factorized Power Architecture (FPA) system
time
time
The VC pin of the PRM should be directly connected to the VC
pin of the VTM. The PRM and VTM coordinate the soft start
sequence of the FPA system through this connection. If the VC
pins are not connected the VTM will not start up. When the
PRM is ready to start up, it applies a voltage on VC, which
enables and powers the VTM’s powertrain. The PRM then
proceeds to ramp up its output voltage. After approximately
10ms, VC returns to 0V and the VTM can then derive power
directly from the factorized bus provided that the factorized bus
voltage is above the minimum specified VTM operating input
voltage when the VC pulse expires.
All VTM faults latch the VTM powertrain off. Input power to the
system as a whole must be recycled or the PRM should be
disabled and enabled by way of its ENABLE pin in order to
restart the system. It is recommended that the voltage on the
factorized bus return to zero before the PRM is re-enabled.
Otherwise the soft start of the system may be compromised.
A RL filter should be placed between the PRM and VTM to
locally isolate switching ripple currents that can interfere with
module operation. It is important that the inductance have an
impedance that is much greater than that of the PRM output
capacitance and VTM input capacitance at the switching
frequencies of the devices. A resistor should be placed in
shunt to this inductor to dampen the resultant LC tank. For
most cases 100nH in parallel with 10Ω is sufficient to isolate
the switching ripple currents.
(a) without Adaptive Loop
(b) with Adaptive Loop
Figure 38 – load step response example and “droop” vs. “kick”
definition. (a) with Adaptive Loop; (b) without Adaptive Loop.
 ^{ln k} ²
_m  100
 ^d
 ^{ln k} ^{2   2}
(11)
 ^d
Burst Mode Operation:
At light loads, the PRM will operate in a burst mode due to
minimum timing constraints. An example burst operation
waveform is illustrated in Figure 39.
For very light loads, and also for higher input voltages, the
minimum time power switching cycle from the powertrain will
exceed the power required by the load. In this case the error
amplifier will periodically drive SHARE/CONROL NODE below
the switching threshold in order to maintain regulation.
Switching will cease momentarily until the error amplifier once
again drives SHARE/CONTROL NODE voltage above the
threshold.
Verifying Stability:
A load step transient response can be used in order to
estimate stability.
Figure 38 illustrates an example of a load step response.
Equation (11) can be used to predict the phase margin based
on the ratio of the “kick” to “droop” (as defined in Fig. 38).
Figure 39 – light load burst mode of operation
- 39 -
Rev. 1.0
11/2012