PI3740-00 Datasheet, PDF (36/48 Pages) Vicor Corporation – Parallel capable with single wire current sharing

L1
VIN ^VS1
C_IN
PGND
VS2 VOUT
PGND
VDR
PGD
EN
SYNCO
SYNCI
TRK
C_TRK
PI3740-00
SGND
ISP
ISN
IMON
VSN
VSP
VDIFF
LGH
EAIN
EAO
COMP
C_COMP
R1
RC
R2
R_LGH
R_SHUNT
CHF
Figure 59 — Lighting Configuration Using CC Mode
When using the CC mode, it is important to set R1 and R2
appropriately to avoid voltage loop interaction with the current
loop. In this case, the voltage setting at the EAIN pin should
be set so that the error between it and the 1.7V reference is
sufficient to force the EAO to be open loop and source current
always. When not using the LGH amplifier, the LGH pin should be
connected to SGND.
The LGH amplifier is able to sink more current than the error
amplifier can source, thus avoiding arbitration issues when
transitioning back and forth from LGH mode to voltage mode.
The equation for setting the source current for EAO is shown
in Equation (14).
I_EAO = (V_EAIN-V_REF) • G_MEA > 400µA
(14)
LGH Amplifier Small Signal Model
A small signal model of the LGH amplifier is shown in Figure 60.
VLGH
RZI
CINT
+
EINT
+
ELS
GMLGH
+
400µA
IEAO
CHF
RZI
CCOMP
ROUT
VEAO
Figure 60 — LGH Amplifier Small Signal Model
The LGH amplifier consists of three distinct stages. The first is
a wide bandwidth integrator stage, followed by a fixed gain
level shift circuit. Finally, the level shift circuit drives a trans-
conductance (TCA) amplifier with an open collector sink only
output stage. Since the LGH output is internally connected to
the output of the voltage error amplifier, the compensation
components show up in the model and are used by both stages,
depending on which one is in use. Only one stage should be in
use at a time. When using LGH or if the LGH input rises above
Cool-Power^® ZVS Switching Regulators
Page 36 of 48
Rev 1.4
04/2017
PI3740-00
the internal reference, the voltage error amplifier acts as a 400µA
current source pull up for the EAO pin.
The integrator pole is determined by the external input resistor
R_LGH and the internal C_INT, which is 20pF. Assuming R_LGH = 100k
and E_INT = 100000:
FpEint =
1
= 0.795Hz (15)
2 • π • (R_LGHT • C_INT • E_INT)
Figure 58 shows a small signal model of the modulator gain
when using the application circuit shown in Figure 59 with
two high current LED’s in series. R_LED is the series combination
of the AC resistance of each LED. R_SHUNT is used to sense the
current through the LED string. Equation (16) defines the pole of
transfer function.
Fpled =
1
(16)
2 • π • ((R_LED + R_SHUNT)//r_EQ • C_OUT
When regulating in CC mode, it will be necessary to add a
compensating zero to avoid loss of phase margin caused by the
integrator stage of the LGH amplifier. A simple approach is to
add a series R–C in parallel with R_LGH as shown in the lighting
application diagram in Figure 59. The capacitor will be chosen
to work with R_LGH to add a zero approximately 1.2kHz before
the zero provided by the GM_LGH transfer function (the trans-
conductance stage of the LGH amplifier). The external added
resistor will form a high frequency pole to roll the gain off at
higher frequency. Note that it is very important to understand the
AC resistance of the LED’s that are being used. Please consult the
LED manufacturer for details. For a series string, you should add
the individual LED resistances and combine them into one lumped
value to simplify the analysis.
VDR Bias Regulator
The VDR internal bias regulator is a ZVS switching regulator that
resides internal to the PI3740-00 SiP. It is intended primarily to
power the internal controller and driver circuitry. The power
capability of this regulator is sized only for the PI3740-00, with
adequate reserve for the application it was intended for. It may be
used as a pull-up source for open collector applications and for
other very low power uses with the following restrictions:
nnThe total external loading on VDR must be less than 2mA.
nnNo direct connection is allowed. Any noise source that can
disturb the VDR voltage can also affect the internal controller
operation. A series impedance is required between the VDR pin
and any external circuitry.
nnAll loads must be locally decoupled using a 0.1µF ceramic
capacitor. This capacitor must be connected to the VDR output
through a series resistor no smaller than 1kΩ, which forms a
low pass filter.
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