PI3740-00 Datasheet, PDF (34/48 Pages) Vicor Corporation – Parallel capable with single wire current sharing

Parallel Operation
PI3740-00 can be connected in parallel to increase the output
capability of a single output rail. When connecting modules in
parallel, each EAO, TRK, EAIN and EN pin should be connected
together. Current sharing will occur automatically in this manner
so long as each inductor is the same value. A common viewing
chain may be used to sense the output voltage. Up to three
modules may be connected in parallel. The modules current
sharing accuracy is determined by the inductor tolerance
(±10%) and to a lesser extent, timing variation (±1.5%). Current
sharing may be considered independent of synchronization
and/or interleaving. Modules do not have to be interleaved
or synchronized to share current. The following equation
determines the output capability of N modules (up to three)
to be determined:
( ) ^I_array ^{= I}_mod ^{+ I}_mod ^{• (N – 1) • 0.77}
(9)
Where:
I_array is the maximum output current of the array
I_mod is the maximum output per module
N is the number of modules
2.5kΩ
L1
CIN
VIN ^VS1
PGND
VS2 VOUT
PGND
COUT
R1
ISP
R2
ISN
VDR PI3740-00 IMON
VSN
VSP
PGD
VDIFF
EN
LGH
SYNCO
EAIN
SYNCI
EAO
TRK
SGND
COMP
CHF
CTRK
CCOMP
L2
VIN ^VS1
PGND
VS2 VOUT
PGND
ISP
ISN
VDR PI3740-00 IMON
VSN
VSP
PGD
VDIFF
EN
LGH
SYNCO
EAIN
SYNCI
EAO
TRK
SGND
COMP
CHF2
CTRK2
CCOMP2
Figure 56 — PI3740-00 parallel operation
PI3740-00
Synchronization
PI3740-00 units may be synchronized to an external clock by
driving the SYNCI pin. The synchronization frequency must not
be higher than 110% of the programmed maximum value F_SW.
This is the switching frequency during DCM of operation. The
minimum synchronization frequency is F_SW / 2. In order to ensure
proper power delivery during synchronization, the user should
refer to the switching frequency vs. output current curves for the
load current, output voltage and input voltage operating point.
The synchronization frequency should not be lower than that
determined by the curve or reduced output power will result.
The power reduction is approximately the ratio between required
frequency and synchronizing frequency. If the required frequency
is 1MHz and the sync frequency is 600KHz, the user should
expect a 40% reduction in output capability.
Interleaving
Interleaving is primarily done to reduce output ripple and the
required number of output capacitors by introducing phase
current cancellation. The PI3740-00 has a fixed delay that is
proportional to to the maximum value of F_SW shown in the
datasheet. When connecting two units as showin in
Figure 56, they will operate at 180 degrees out of phase when the
converters switching frequency is equal to F_SW. If the converter
enters CrCM and the switching frequency is lower than F_SW, the
phase delay will no longer be 180 degrees and ripple cancellation
will begin to decay. Interleaving when the switching frequency is
reduced to lower than 80% of the programmed maximum value
is not recommended. Operation over high boost ratios such as
8V in to 36V out or narrow buck ratios like 28V in to 24V is not
recommended for interleaving.
Cool-Power^® ZVS Switching Regulators
Page 34 of 48
Rev 1.4
04/2017
vicorpower.com
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