PI352X-00 Datasheet, PDF (28/34 Pages) Vicor Corporation – 30VIN to 60VIN Cool-Power ZVS Buck Regulator

Parallel Operation
Multiple PI352x-00 can be connected in parallel to increase
the output capability of a single output rail. When connecting
modules in parallel, each EAO, TRK, and EN pin should be
connected together. EAIN pins should remain separated, each
with an REA1 and REA2, to reject noise differences between
different modules' SGND pins. Current sharing will occur
automatically in this manner so long as each inductor is the same
value. Refer to the Electrical Characteristics table for maximum
array size and array rated output current. Current sharing may be
considered independent of synchronization and/or interleaving.
Modules do not have to be interleaved or synchronized
to share current.
V_IN
EN
CIN_1
VIN
VS1
ZVS-Buck VOUT
PGND
VDR
#1
VSP
VSN
SYNCO
VDIFF
SYNCI
TRK
PWRGD
EAIN
EN
EAO
TESTx
COMP
SGND
L1_1
COUT_1
V_OUT
TRK
EAO
REA1_1
REA2_1
CCOMP_1
V_IN
EN
CIN_2
VIN
VS1
ZVS-Buck VOUT
PGND
VDR
#2
VSP
VSN
SYNCO
VDIFF
SYNCI
TRK
PWRGD
EAIN
EN
EAO
TESTx
COMP
SGND
L1_2
COUT_2
V_OUT
TRK
EAO
REA1_2
REA2_2
CCOMP_2
Figure 61 — PI352x-00 parallel operation
Due to the high output current capability of a single module and
Critical Conduction Mode (CrCM) occurring at approximately
50% rated load, interleaving is not supported.
Use of the PI352x-00 SYNCI pin is practical only under a limited
set of conditions. Synchronizing to another converter or to a fixed
external clock source can result in a significant reduction in output
power capability or higher than expected ripple.
Filter Considerations
The PI352x-00 requires low impedance ceramic input capacitors
(X7R/X5R or equivalent) to ensure proper start up and high
frequency decoupling for the power stage. The PI352x-00
will draw nearly all of the high frequency current from the
low impedance ceramic capacitors when the main high side
MOSFET(s) are conducting. During the time the MOSFET(s) are off,
the input capacitors are replenished from the source.
Table 6 shows the recommended input and output capacitors
to be used for the PI352x-00 as well as per capacitor RMS ripple
current and the input and output ripple voltages. Table 5 lists the
recommended input and output ceramic capacitors manufacturer
and part numbers. It is very important to verify that the voltage
supply source as well as the interconnecting lines are stable and
do not oscillate.
PI352x-00
Input Filter Case 1 — Inductive source and local, external,
input decoupling capacitance with negligible ESR
(i.e.: ceramic type):
The voltage source impedance can be modeled as a series
R_line L_line circuit. The high performance ceramic decoupling
capacitors will not significantly damp the network because
of their low ESR; therefore in order to guarantee stability the
following conditions must be verified:
( ) ^{Rline >}
L_line
C + C _{IN_INT}
IN_EXT
• r_{EQ_IN}
(5)
R_line << r_{EQ_IN}
(6)
Where r_{EQ_IN} can be calculated by dividing the lowest line voltage
by the full load input current. It is critical that the line source
impedance be at least an octave lower than the converter’s
dynamic input resistance, Equation (6). However, R_line cannot
be made arbitrarily low otherwise Equation (5) is violated and
the system will show instability, due to an under-damped
RLC input network.
Input Filter case 2 — Inductive source and local, external
input decoupling capacitance with significant R_{CIN_EXT} ESR
(i.e.: electrolytic type):
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor L_line.
Notice that the high performance ceramic capacitors C_{IN_INT}
within the PI352x-00 should be included in the external
electrolytic capacitance value for this purpose. The stability
criteria will be:
r > R _{EQ_IN}
CIN_EXT
(7)
L_line
C • R _{IN_INT}
CIN_EXT
<
r_{EQ_IN}
(8)
Equation (8) shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (C_{IN_EXT}) – the
system will be under-damped and may even become destabilized.
As noted, an octave of design margin in satisfying Equation (7)
should be considered the minimum. When applying an electrolytic
capacitor for input filter damping the ESR value must be chosen to
avoid loss of converter efficiency and excessive power dissipation
in the electrolytic capacitor.
Cool-Power^® ZVS Switching Regulators
Page 28 of 34
Rev 1.3
06/2017
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