PRM48DH480T250A03 Datasheet, PDF (22/23 Pages) Vicor Corporation – Building block for high efficiency DC-DC systems

PRM48DH480T250A03
9.5.2 Inductive source and local, external input
decoupling capacitance with significant R_{CIN_EXT} ESR (i.e.:
electrolytic type)
In order to simplify the analysis in this case, the voltage
source impedance can be modeled as a simple inductor
L_line. Notice that, the high performance ceramic capacitors
C_{IN_INT} within the PRM should be included in the external
electrolytic capacitance value for this purpose. The
stability criteria will be
r > R _{EQ_ IN}
C_{IN _ EXT}
[8]
L_line
C ⋅ R ^{< r} _{IN _ EXT}
C_{IN _ EXT}
EQ _ IN
[9]
Equation [9] shows that if the aggregate ESR is too small
– for example by using very high quality input capacitors
(C_{IN_EXT}) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying [8] should be considered the minimum.
9.6 Arrays
Up to ten PRMs of the same type may be placed in
parallel to expand the power capacity of the system. The
following high-level guidelines must be followed in order
for the resultant system to start up and operate properly,
and to avoid overstress or exceeding any absolute
maximum ratings.
Ø –IN pins of all PRMs must be connected together.
Both inductance and resistance from the common
power source to each PRM should be minimized,
and matched.
Ø Input voltage to all PRMs must be the same.
Independent fuses for each PRM are
recommended.
Ø PC pins must be connected together for
synchronization and proper fault response.
Ø Reference supply to the control loop voltage
reference and current sense circuitry must be
enabled when all modules’ RE pins have reached
their operational voltage levels.
Ø There must be one single external voltage control
loop. The control loop must drive each PR pin
relative to each module’s SG pin, and the local PR
voltage must be the same across all modules.
Ø Each PRM must have its own local current shunt
and current sense circuitry to drive its IF pin.
Ø The number of PRMs required to achieve a given
array capacity must consider all sources of
mismatch to avoid overstress of any PRM in the
array. Imbalances in sharing are not only due to
current sharing accuracy specifications, but also
temperature differences among PRMs, Vin
variations, and error terms in the buffering of the
error amplifier output to the PR pins.
Ø Control loop compensation procedures above will
hold for an array, in general, although many
parameters must be scaled against the number of
PRMs in the system.
Please contact Vicor Applications for assistance.
9.7 Input Fuse Recommendations
A fuse should be incorporated at the input to each PRM, in
series with the +IN pin. A 10 A or smaller input fuse
(Littelfuse^® NANO^2® 451/453 Series, or equivalent) is
required to safety agency conditions of acceptability.
Always ascertain and observe the safety, regulatory, or
other agency specifications that apply to your specific
application.
9.8 Layout considerations
Application Note AN:005 details board layout using V•I
Chip components. Additional consideration must be given
to the external control circuit components.
The current sense shunt signal voltage is highly sensitive
to noise. As such, current sensing circuitry should be
located close to the shunt to minimize the length of the
sense signals. A Kelvined connection at the shunt is
recommended for best results.
The control signal from a remote voltage sense circuit to
the PRM should be shielded. Avoid routing this, or other
control signals directly underneath the PRM, if possible.
Components that tie directly to the PRM should be located
close to their respective pins. It is also critical that all
control components be referenced to SG, and that SG not
be tied to any other ground in the system, including –IN or
–OUT of the PRM.
PRM^® Regulator  
 
Rev 1.4  
 
vicorpower.com  
Page 22 of 23    
 
12/2012    
 
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